The present invention relates to integrated circuits and more particularly to capacitor structures for an integrated circuit and methods of manufacture therefor.
Capacitors are used in integrated circuit designs to achieve different functions such as dynamic random access memories, bypassing, and filters. Conventionally, a capacitor in an integrated circuit is composed of two flat conductive plates, with one on the top of the other, and an intervening layer of dielectric material. One disadvantage of this structure is the relatively large area of the chip which is required to obtain the desired capacitance.
One approach to reducing the required chip area involves stacking several layers of conductive plates, which are alternately connected to form opposite electrodes of the capacitor. However, such structure requires additional processing steps during the integrated circuit fabrication process resulting in an associated increase in the cost of manufacture.
Another approach to reducing the required chip area involves the use of a layer of parallel interdigitated strips as electrodes having a dielectric material therebetween. Such a structure provides higher capacitance value per unit area, as a result of the increased electrode (plate) area afforded by the opposing top bottom and sidewall surfaces.
As illustrated in FIG. 1, prior art interdigitated capacitors have parallel strips 130, 140, 150, 160 in the first layer 100, which are alternately connected to the first bus 110 and second bus 120. Strips 130 and 150 are connected to the first bus 110 with the same polarity. Strips 140 and 160 are connected to the second bus 120 with the opposite polarity to the first bus 110. At least one more layer of the same structure overlies the first layer. FIG. 2 shows the structure in cross section through the strips. As shown in FIG. 3, the first buses 310, 312, 314, and 316 and second buses 320, 322, 324, and 326 of different layers are respectively connected by vias 330 and 340. Dielectric material is filled between strips of the same and different layers.
However, since the interdigitated fingers of each layer are parallel to each other in this structure, any misalignment of strips from one layer to the next, caused, for example, by overall registration errors, will change relative positions between the electrodes. As a result, the overall capacitance of the structure will deviate from the expected value and affect the performance of the integrated circuit. As illustrated in FIG. 4, one disadvantage of prior art interdigitated capacitors is the undesired variance of capacitance caused by misalignment of strips between adjacent layers, such as between 412 and 422, because capacitance varies when the relative position between parallel strips of two adjacent layers changes. It is desirous therefore to reduce variation in capacitance value of such a structure resulting from interlayer misalignment.
The present invention provides a capacitor structure for an integrated circuit comprising at least two layers of substantially parallel interdigitated strips wherein the strips of each layer are alternately connected to a first bus and a second bus. The first and the second bus of each layer are respectively interconnected to the first and second bus of an adjacent layer. The strips of each layer are oriented approximately perpendicular to the strips of an adjacent layer. The capacitor structure further comprises dielectric material between strips of the same and different layers.
Further, the present invention includes a method of fabricating the capacitor structure. The method comprises forming at least two layers of substantially parallel interdigitated strips which are alternately connected to a first bus and a second bus of each layer. Respectively connecting the first and the second bus of each layer to the first and the second bus of an adjacent layer. Orienting the strips of one layer approximately perpendicular to the strips of an adjacent layer. And, forming dielectric material between strips of the same and different layers.